1. Field of the Invention
The present invention relates to a microprocessor memory bus interface, and more particularly, to an interface which minimizes the amount of address latching so as to save clock cycles during memory data transfer.
2. Description of the Prior Art
Interfacing a microprocessor with a memory device is accomplished in a number of ways. Special interfacing techniques have been developed in the prior art when the microprocessor and memory device have different addressable data sizes. For example, a 32-bit word microprocessor is interfaced with 16-bit word memory chips in an IBM PC by performing two memory accesses to the 16-bit memory and forming a 32-bit data word acceptable to the microprocessor. One of the benefits of such an interface is that hardware cost is reduced since the number of dynamic random access memory chips is reduced. However, the overall performance of the computer usually suffers as a result of the reduced hardware support.
A decline in the overall performance is generally caused by increased overhead tasks. In the above-mentioned system, the interface has to coordinate extra intermediate steps that do not exist where the same task is directly accomplished. For example, the microprocessor of the aforementioned system thinks that it is writing a 32-bit word at a single address in the memory device. However, since the interface has to write the data at two memory addresses in the 16-bit addressable memory device, the interface has to temporarily hold the 32-bit word before writing two 16-bit words at adjacent memory addresses in the memory device. As a result, one write operation to the microprocessor is actually two write operations to the interface, and the coordination of such write operations requires a controller to handle the overhead. Similarly, during a read operation, a 32-bit word is read from two 16-bit words in the memory device. The two 16-bit words are sequentially read from the temporary media and must be held until the microprocessor can simultaneously read them. Again, the coordination of sequential read operations requires some overhead.
FIG. 1 illustrates a prior art microprocessor 100 interfaced with a memory device 102 whose addressable data size is smaller than that of the microprocessor 100. For example, the microprocessor 100 may be a 64-bit INTEL i860 microprocessor, while the memory device 102 may be a 32-bit DRAM (Dynamic Random Access Memory). The interface comprising transceivers 104 and 106 and control device 108 makes the 32-bit DRAM 102 appear to microprocessor 100 as a sequence of 64-bit wide locations by packing two 32-bit words into one 64-bit word for i860 reads from transceivers 104 and 106 and unpacking one 64-bit word into two 32-bit words of transceivers 104 and 106 for i860 writes. The packing and unpacking is controlled by control device 108.
Control device 108 controls packing and unpacking by asserting a variety of signals: LtchBA latches the data from microprocessor 100 to transceivers 104 and 106 on its rising edge; nLOEBA enables lower transceivers 106 to drive their contents onto the data bus connecting to memory device 102; nUOEBA enables upper transceivers 104 to drive their contents onto the data bus connecting to memory device 102; UWdLtch latches the data from memory device 102 to upper transceivers 104 on its rising edge; LWdLtch latches the data from memory device 102 to lower transceivers 106 on its rising edge; and OEAB enables both lower and upper transceivers 106 and 104 to drive their contents onto the data bus connecting to microprocessor 100.
During i860 write cycles, control device 108 asserts the following signals. IData[63:0] is latched to transceivers 104 and 106 on the rising edge of LtchBA. As a result, the upper transceivers 104 hold the data bits 32 through 63, while the lower transceivers 106 hold the data bits 0 through 31. nLOEBA is then asserted causing the lower transceivers 106 to drive IData[31:0] onto XData[31:0]. A DRAM write cycle is then initiated which writes XData[31:0] to the lower (IAddr[2]=0) DRAM address. Then after nLOEBA has been negated long enough to avoid bus contention between upper and lower transceivers 104 and 106, nUOEBA is asserted allowing the upper transceivers 104 to drive IData[63:32] onto XData[31:0]. A DRAM write cycle is then initiated which writes XData[31:0] to the upper (IAddr[2]=1) DRAM address.
During i860 read cycles, control device 108 asserts the following signals. XData[31:0] is latched into the lower transceivers 106 on the rising edge of LWdLtch. When the data from the next address (IAddr[2]=1) is valid on XData[31:0], it is latched into the upper transceivers 104 on the rising edge of UWdLtch. Both lower and upper transceivers are then enabled, by asserting OEAB, driving data onto IData[63:0], which is then read by the i860.
Overhead tasks also include the coordination of address latching. Although not shown in FIG. 1, the generated address is first latched in an address latch. Since the accesses are 32-bits wide, only address bits 19 through 2 need to be used, and accordingly, address bit 2 must be generated to compensate for a one-bit address shift in the address latch. The address is then relatched in the memory device 102 before data in the memory device 102 is finally accessed. Therefore, an address must be latched twice for each read and write operation. It is desired to minimize some of this excess address latching so that some processing cycles may be saved during memory access.
A need thus exists for an interface unit which can reduce the hardware cost by interfacing a microprocessor with an inexpensive memory device with a smaller word size without compromising the overall performance. One object of the current invention is to improve the overall performance of the interface system by reducing the overhead address relatch described above without adding expensive and sophisticated pieces of hardware. The present invention fulfills these objects.